Fakulta elektrotechnická

České vysoké učení technické v Praze

ČVUT v Praze

Popis předmětu - AE4M34ISC

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AE4M34ISC Systems on Chip Rozsah výuky:2+2C
Garanti:Jakovenko J. Role:PO,V Zakončení:Z,ZK
Vyučující:Jakovenko J., Janíček V.
Zodpovědná katedra:13134 Kreditů:6 Semestr:L

Anotace:

Main responsibilities of integrated circuits designer; design abstraction levels - Y chart. Specification designation, feasibility study, criteria for technology and design kits selection. Analogue and digital integrated systems design and simulation methodologies. Main features of application specific ICs - full custom design, gate arrays, standard cells, programmable array logic. Design aspects mobile and low power systems. Hardware Description languages (HDL). Logic and physical synthesis. Frond End and Back End design. Floorplanning, place and route, layout, parasitic extraction, time analysis, testbenche construction and verification.

Výsledek studentské ankety předmětu je zde: AE4M34ISC

Osnovy přednášek:

1. Main tasks of analogue and digital integrated circuits designer; design methodologies (top down, bottom up), design abstraction levels - Y chart.
2. Application specific integrated circuits systems types, full custom design, gate array, standard cells, programmable array logic; main features, economical aspect of the design.
3. Full customs integrated systems, feasibility study, specification, criteria for technology and design kits selection.
4. World standards and CAD tools for analog and mix-signal integrated circuits design, design of RF and mobile low power systems.
5. Design tools for automatic generation of analog behavior models, bottom up design methodology, macro blocks.
6. Design principles of mix-signal integrated circuits, purpose of hierarchical design, digital and analogue block interface, CAD design tools for automatic circuit generation; functional and static time analysis, formal verification; Verilog-A, Verilog-AMS, VHDL-A.
7. Hardware description languages -VHDL, Verilog, Verilog-A, Verilog-AMS.
8. Design tools and methodologies for digital integrated circuits and systems; language VHDL, Verilog; library cells; parameters extractions for library cells development.
9. Frond end design - functional specification, RTL, logic synthesis, Gate-level netlist, behavioral stimulus extraction.
10. Back End design - specification of Design Kit, mapping of the design, Floorplanning, place and route, layout, parasitic extraction, layout versus schema check (LVS).
11. Methods of physical synthesis, placement of functional blocks, power lines design and distribution, simulation of interconnect continuity, design verification.
12. Clock signal distribution, delay calculating, static and dynamic timing analysis.
13. Testing, design of testbenches, design verification methods.
14. Tape out and fabrication, integrated systems verification, scaling and design mapping to different technologies.

Osnovy cvičení:

1. CADENCE design system
2. CMOS Design kit description, library cells
3. Demonstration of mix-signal design - hierarchical structuring, design cells abstraction.
4. Demonstration of mix-signal design - simulations, interface definition, Spectre AMS simulator, corner analysis.
5. Analogue layout, parasitic extraction, design rule check, postlayout simulation.
6. Demonstration of mix-signal design - digital flow, back end, frond end.
7. Digital layout (Back End design), Floorplanning, routing, timing analysis.
8. Student project - design of mix-signal IC.
9. Student project - design of mix-signal IC.
10. Student project - design of mix-signal IC.
11. Student project - design of mix-signal IC.
12. Student project - design of mix-signal IC.
13. Student project - design of mix-signal IC.
14. Student project presentation, final assessment.

Literatura:

Michael Smith: Application-Specific Integrated Circuits, Addison-Wesley, 1998
P. Gray, P Hurst, s. Lewis, R. Mayer: Analysis and Design of Analog
Integrated Circuits, John Wiley and Sons, 2000
E. Sinencio, A. Andreou: Low-Voltage/Low-Power Integrated Circuits and
Systems, John Wiley and Sons, 1998 Mark Zwolinski : Digital System Design and VHDL , Prentice-Hall, 2000

Požadavky:

https://moodle.kme.fel.cvut.cz/moodle/login/index.php?lang=cs

Poznámka:

Rozsah výuky v kombinované formě studia: 14p+6l

Klíčová slova:

System on Chip, IC Design

Předmět je zahrnut do těchto studijních plánů:

Plán Obor Role Dop. semestr
MEKME4 Sítě elektronických komunikací V 2
MEKME5 Komunikační systémy V 2
MEKME3 Elektronika V 2
MEKME2 Multimediální technika V 2
MEKME1 Bezdrátové komunikace V 2
MEOI2 Počítačové inženýrství PO 2
MEEEM3 Elektroenergetika V 2
MEEEM4 Ekonomika a řízení energetiky V 2
MEEEM5 Ekonomika a řízení elektrotechniky V 2
MEEEM1 Technologické systémy V 2
MEEEM2 Elektrické stroje, přístroje a pohony V 2
MEKYR4 Letecké a kosmické systémy V 2
MEKYR1 Robotika V 2
MEKYR2 Senzory a přístrojová technika V 2
MEKYR3 Systémy a řízení V 2


Stránka vytvořena 17.11.2017 17:47:23, semestry: L/2016-7, Z,L/2017-8, Z/2018-9, připomínky k informační náplni zasílejte správci studijních plánů Návrh a realizace: I. Halaška (K336), J. Novák (K336)
Za obsah odpovídá: doc. Ing. Ivan Jelínek, CSc.